CYCLE_CNT_INT=Val_0x0, EVENT_CNT_1_INT=Val_0x0, EVENT_CNT_3_INT=Val_0x0, EVENT_CNT_2_INT=Val_0x0, EVENT_CNT_0_INT=Val_0x0
Performance Monitor Interrupt Clear Register
| EVENT_CNT_0_INT | Disable overflow interrupt request for PMU event counter 0. overflow interrupt request. 0 (Val_0x0): When read, it means the event counter overflow interrupt-request is disabled. When written, it has no effect. 1 (Val_0x1): When read, it means the event counter overflow interrupt-request is enabled. When written, it disables the event count |
| EVENT_CNT_1_INT | Disable overflow interrupt request for PMU event counter 1. overflow interrupt request. 0 (Val_0x0): When read, it means the event counter overflow interrupt-request is disabled. When written, it has no effect. 1 (Val_0x1): When read, it means the event counter overflow interrupt-request is enabled. When written, it disables the event count |
| EVENT_CNT_2_INT | Disable overflow interrupt request for PMU event counter 2. overflow interrupt request. 0 (Val_0x0): When read, it means the event counter overflow interrupt-request is disabled. When written, it has no effect. 1 (Val_0x1): When read, it means the event counter overflow interrupt-request is enabled. When written, it disables the event count |
| EVENT_CNT_3_INT | Disable overflow interrupt request for PMU event counter 3. overflow interrupt request. 0 (Val_0x0): When read, it means the event counter overflow interrupt-request is disabled. When written, it has no effect. 1 (Val_0x1): When read, it means the event counter overflow interrupt-request is enabled. When written, it disables the event count |
| CYCLE_CNT_INT | Disable overflow interrupt request for PMU cycle counter. overflow interrupt request. 0 (Val_0x0): When read, it means the cycle counter overflow interrupt-request is disabled. When written, it has no effect. 1 (Val_0x1): When read, it means the cycle counter overflow interrupt-request is enabled. When written, it disables the cycle count |